Dimin Niu

Matrix: Multi-Cipher Structures Dataflow for Parallel and Pipelined TFHE Accelerator

Jan 1, 2025

H2-LLM: Hardware-Dataflow Co-Exploration for Heterogeneous Hybrid-Bonding-based Low-Batch LLM Inference

Jan 1, 2025

Salus: A Practical Trusted Execution Environment for CPU-FPGA Heterogeneous Cloud Platforms

Jan 1, 2024

A Tightly Coupled AI-ISP Vision Processor

Jan 1, 2024

Tt-gnn: Efficient on-chip graph neural network training via embedding reformation and hardware optimization

Jan 1, 2023

Spada: Accelerating sparse matrix multiplication with adaptive dataflow

Jan 1, 2023

Predicting the output structure of sparse matrix multiplication with sampled compression ratio

Jan 1, 2023

MPU: Memory-centric SIMT processor via in-DRAM near-bank computing

Jan 1, 2023

Mnsim 2.0: A behavior-level modeling tool for processing-in-memory architectures

Jan 1, 2023

Accelerating distributed GNN training by codes

Jan 1, 2023